1. Field of the Invention
The present invention relates to a method of making a shingle stacked die package and, more particularly, to a method of making shingle stacked die packages having a reduced number of processing steps wherein the die are attached by either a thin layer of adhesive or a molecular bonding process to produce an essentially zero bond-line between the bonded die.
2. Brief Description of Related Technology
The use of integrated circuit (IC) chips or dice is widespread in electronics applications. Continuing progress in the manufacture of IC chips has resulted in chips of greatly increased density, i.e., a higher number of semiconductor die per footprint area of each chip. In order to produce increasingly complex electronic structures exhibiting high circuit densities, it has become common practice to stack dice on a lead frame die paddle to create what is known in the art as a multi-chip package or multi-chip module (MCM). A variety of multi-chip package designs are described in U.S. Pat. Nos. 6,514,794 and 6,376,904 each to Haba et al., U.S. Pat. No. 6,621,155 to Perino et al., U.S. Pat. No. 5,495,398 to Takiar et al., U.S. Pat. No. 6,900,528 to Mess et al, and United States Patent Publication No. 2008/0054432 to Corisis et al.
Shingle stack configuration is known in the industry to be an optimum way to achieve a high number of dice in a stack. In a shingle stack, the die overlap, forming a staircase in which the “step” of every die contains the exposed wire bond pads. Typically these stacks are formed by singulating, handling and placing every die one-by-one in a shingle stack assembly. Because of the multiple handling steps of the individual die, this process can be time-consuming and expensive, and can result in damage to the die and/or wafer. As discussed in U.S. Pat. No. 7,217,596, one technique for forming a stacked die module includes providing a stacking tip and sequentially stacking adhesively coated precut die by a “top down” sequence into the stack prior to coupling the die stack to a substrate. These die may be stacked according to a variety of designs including a wedding cake/pyramid design and/or a shingle stacked design. A disadvantage of this process is that it still requires multiple processing and handling steps as the die are individually cut and singly joined with one another.
Cleaving strips of die from a wafer and stacking them is known in the process for coating the mirrors in GaN laser manufacturing. As discussed in the article “Cleaving Strips of Die From a Wafer In GaN Laser Manufacturing” published in Compound Semiconductor, July 2005, pages 16-17, this process includes coating the exposed edges of the stacked strips to form the mirrors, unstacking the strips for testing, and then cutting the strips into separate die.
Semiconductor die or chips are typically produced from a wafer containing a plurality of individual circuits spaced apart by streets. During the back end processing phase of the packaging portion of the production, this wafer is cut along the streets into individual die, which are then stacked and bonded to one another and/or to a substrate. This bonding is typically achieved through the use of a paste-type adhesive. This paste-type adhesive would be dispensed onto a die, a second die would be positioned thereon and the adhesive cured. Problems associated with the use of paste adhesives, such as unwanted flowing of the adhesive, caused the industry to develop alternative bonding methods. These alternative bonding methods include the use of pressure sensitive adhesives or film adhesives mounted on a carrier tape. The use of the adhesives currently in the market typically produce a bond-line thickness of approximately 25 μm between the die.
Semiconductor fabrication generally involves two types of operations: front end processing and back end processing. The “front end” processing typically refers to the steps involved with creating the circuitry prior to individualizing the integrated circuit chips, such as formation of transistors directly on the silicon wafer, surface engineering including formation of gate dielectric such as silicon dioxide, and interconnecting electrical circuits to form individual integrated circuit chip dies. The “back end” processing involves packaging of the individual chip dies thus formed. This is typically accomplished by mounting the die to a substrate such as a circuit board, and/or mounting a number of die to each other in the stacked die construction. Such mounting traditionally involves electrically connecting pads on the die to pads on the substrate to form the package such as through wire bonding. Typically adhesives are used for mounting the die to the substrate or another die. Additional adhesive materials are used to encapsulate the final construction in order to create the integrated package.
In view of the ever-decreasing size of circuits, new techniques are constantly being developed for decreasing chip thicknesses and producing more compact electrical components. Thus, there is a need for processes that enable the stacking of more die in a limited amount of vertical height. One way this can be achieved is by making the die thinner than previously used, even as thin as 2 μm. With the chip thickness being decreased, the bonding of the chips together must also be decreased. This is difficult to achieve through the use of traditional adhesives and bonding techniques currently in employed in this industry.
Bonding techniques to produce essentially zero bond-lines are known in the semi-conductor wafer processing industry in the “front end” processing of the semiconductor wafer in the area of photonics. As stated above, “front end” processing refers to the steps involved with creating the circuitry prior to individualizing the integrated circuit chips. Photonic integrated circuits offer the potential of realizing low-cost, compact optical functions. As discussed in the article entitled “III-V/Si Photonics by Die-to-Wafer Bonding” published in Materials Today, July-August 2007, Volume 10, Number 7-8, there are three main routes to the integration of III-V material on top of an SOI (silicon-on-insulator) layer, namely, flip-chip integration, heteroepitaxial growth, and bonding technology. The flip-chip technique has disadvantages in terms of processing times and production costs. The heteroepitaxial growth technique has encountered problems in terms of limited integration density and is hampered by the large lattice mismatch of 8% between the III-V material and the Si host substrate. This leads to large threading and misfit dislocation densities in the grown layers and deterioration of the optical properties. The final route, semiconductor wafer bonding, allows the integration of high-quality III-V epitaxial layers on top of a Si platform by transferring the III-V layer stack from its original growth substrate to the SOI wafer. To decrease the cost of the integration process, in terms of both time and consumption of expensive III-V material, a die-to-wafer bonding process has been proposed in which unprocessed InP/InGaAsP dies are bonded, epitaxial layers down, to the processed SOI wafer. This technique reduces material consumption, as III-V semiconductors are only bonded where they are needed, and reduces the time required to complete the integration process compared with a flip-chip process as only limited alignment accuracy is needed. The article discusses two techniques for semiconductor wafer bonding that have been investigated. The first of these techniques is through the use of a thermosetting polymer adhesive acting as a bonding agent. The second technique utilizes molecular bonding between the layers. In this second technique, the SOI (silicon-on-insulator) wafer surface is coated with an SiO2 cladding layer and planarization is achieved by chemical mechanical polishing (CMP). Subsequently, the III-V epitaxial layer structure is coated with SiO2 and, if needed, a touch-polish (CMP) polishing step can be used to reduce the surface microroughness to an amount necessary to achieve molecular bonding. The surfaces of both wafers must be in contact on the atomic scale, which requires a root mean squared microroughness of approximately 0.5 nm to achieve molecular adhesion. After surface planarization and reduction of the microroughness, both wafer surfaces are chemically activated to make them hydrophilic. This can be achieved by wet chemical treatment or plasma activation. Van der Waals interactions between both surfaces is achieved when the two activated wafer surfaces are attached to each other because of the presence of a water interface layer, which is readily adsorbed at the wafer surface. During high temperature annealing of the bonded stack, water molecules are removed from the bonding interface, leaving a covalent bond between the SiO2 surfaces. This process requires high temperature processing in excess of 300° C. to drive the moisture or water out during the annealing process to form a SiO/Si ceramic or inorganic bond.
As shown in FIG. 1, a conventional process includes cleaving strips 12 of die 14 from a wafer 10 and stacking the strips 16. As discussed in the article “Cleaving Strips of Die From a Wafer In GaN Laser Manufacturing” published in Compound Semiconductor, July 2005, pages 16-17, this process includes coating the exposed edges 18 of the stacked strips 16 to form the mirrors, unstacking the strips for testing 20, and then cutting the strips 16 into separate die 22.
During the “back end” processing and packaging of semiconductor die, high temperature processing must be avoided. Temperatures in excess of 200° C., and in some instances greater than 175° C., can cause damage to the substrate and undesirable solder reflow of the solder balls placed on the ball-grid-array (BGA) used for interconnecting with the circuit board substrate. Accordingly, conventional molecular bonding techniques involving high temperatures, such as those described for use in the front end wafer processing, cannot be used in the back end die attach/packaging processing.
There is a need in the art to replace the process steps of singulating, handling, and placing every die one-by-one in a shingle stack assembly with a more time efficient process of stacking of strips and then cutting into individual die stacks, which reduces the amount of handling of the individual die. There is a further need in the art for a “back-end” processing environment to produce a molecular bond having a thin (0.1-5 μm) bond-line thickness between the die, thereby increasing the number of die in a stack within a limited amount of vertical height.